Reduction in device sizes is a key goal of improving semiconductor processes. Amazingly small transistor devices have been produced. These extremely tiny transistors have thin oxide that can be easily damaged by relatively small currents with even a moderate driving force (voltage). Special care is required when a human handles these semiconductor devices.
Static electricity that normally builds up on a person can discharge across any pair of pins of a semiconductor integrated circuit (IC or chip). IC chips are routinely tested for resistance to such electrostatic discharges (ESD) using automated testers that apply a Human-Body Model (HBM) current pulse across different pairs of pins of the chip. Any pair of pins may be chosen for the ESD test.
While input and output pins were originally provided with ESD-protection circuits, the core circuitry was directly connected to the Vdd power supply and the Vss ground supply without a power clamp for ESD protection. When an ESD pulse is applied between Vdd and Vss, the internal circuit may be damaged by the ESD pulse.
ESD protection circuits with thick oxide transistors have been used. Thick-oxide transistors are less sensitive to damage than thin-oxide transistors. In the power clamp, large transistors with gate widths of 1,000 to 5,000 μm have been used for protection. Such large transistors are usually a Field-Effect Transistor (FET) and are referred to as a BigFET.
Rather than use passive circuits, an active clamp may also be used. FIG. 1 shows a prior art power-to-ground ESD protection circuit with an active R-C triggered BigFET power clamp.
An R-C sensing element is formed by capacitor 22 and resistor 20. Inverters 10, 12, 14 invert the sensed voltage between capacitor 22 and resistor 20, and drive the gate of n-channel power clamp BigFET 18.
Under normal conditions, resistor 20 drives the input of inverter 10 high, causing a low to be driven onto the gate of n-channel BigFET 18, keeping it off. When the power-to-ground voltage suddenly spikes high, such as during an ESD event, capacitor 22 keeps the input of inverter 10 low for a period of time determined by the R-C time constant. The low input to inverter 10 drives the gate of n-channel BigFET 18 high, turning on n-channel BigFET 18 and shunting current from power to ground, dissipating the ESD pulse applied to the power line.
While such an active ESD-protection circuit is useful, it may be susceptible to noise, especially during power-up of the chip. If the active ESD-protection circuit triggers during power-up, excessive current may be drawn through the clamp transistor, resulting in big leakage or even Latch-up.
After the R-C time period has elapsed, resistor 20 pulls the input to inverter 10 high, and a low is driven onto the gate of n-channel BigFET 18, turning it off. If the R-C value is too small, the clamp turns off too soon, before all the ESD charge can be shunted to ground through n-channel BigFET 18. For the HBM, the pulse width is relatively wide, so a large R-C value (such as about 1 μs) is needed so that n-channel BigFET 18 does not turn off before the end of the HBM ESD pulse. This large R-C value results is a large size for capacitor 22. Leakage and false triggering can be a problem with the large capacitor.
Capacitor 22 may have a value of around 10 pF. The circuit of FIG. 1 may require an area of 12,000 μm2 for a 0.35-μm CMOS process. Feedback, bistable elements, and thrysistors have been used to solve the large capacitor problem of FIG. 1. However, improved feedback circuits are still desirable.
What is desired is an ESD-protection circuit that protects the internal power supplies of an IC. An active rather than a passive protection circuit is desired. It is desired to actively enable or disable the ESD-protection circuit. It is desired to actively enable and disable a BigFET as an ESD current shunt between power and ground rings. An active ESD-protection circuit that is insensitive to noise during power up is desired. An ESD-protection circuit with improved feedback is desired to reduce the size of the capacitor. A smaller time constant and capacitor is desirable for an active clamp.